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19-5400; Rev 0; 9/00
KIT ATION EVALU BLE AVAILA
10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference
General Description
The MAX1448 +3V, 10-bit analog-to-digital converter (ADC) features a fully differential input, a pipelined 10stage ADC architecture with wideband track-and-hold (T/H), and digital error correction incorporating a fully differential signal path. The ADC is optimized for lowpower, high dynamic performance in imaging and digital communications applications. The converter operates from a single +2.7V to +3.6V supply, consuming only 120mW while delivering a 59dB (typ) signal-tonoise ratio (SNR) at a 20MHz input frequency. The fully differential input stage has a -3dB 400MHz bandwidth and may be operated with single-ended inputs. In addition to low operating power, the MAX1448 features a 5A power-down mode for idle periods. An internal +2.048V precision bandgap reference is used to set the ADC full-scale range. A flexible reference structure allows the user to supply a buffered, direct, or externally derived reference for applications requiring increased accuracy or a different input voltage range. Lower speed, pin-compatible versions of the MAX1448 are also available. Please refer to the MAX1444 data sheet for a 40Msps version and to the MAX1446 data sheet for a 60Msps version. The MAX1448 has parallel, offset binary, CMOS-compatible three-state outputs that can be operated from +1.7V to +3.6V to allow flexible interfacing. The device is available in a 5mm x 5mm 32-pin TQFP package and is specified over the extended industrial (-40C to +85C) temperature range. o Single +3.0V Operation o Excellent Dynamic Performance 59dB SNR at fIN = 20MHz 74dBc SFDR at fIN = 20MHz o Low Power 40mA (Normal Operation) 5A (Shutdown Mode) o Fully Differential Analog Input o Wide 2Vp-p Differential Input Voltage Range o 400MHz -3dB Input Bandwidth o On-Chip +2.048V Precision Bandgap Reference o CMOS-Compatible Three-State Outputs o 32-Pin TQFP Package
Features
MAX1448
Ordering Information
PART MAX1448EHJ TEMP. RANGE -40C to +85C PIN-PACKAGE 32 TQFP
Functional Diagram
________________________Applications
Ultrasound Imaging CCD Imaging Baseband and IF Digitization Digital Set-Top Boxes Video Digitizing Applications
CLK MAX1448 CONTROL
VDD GND
IN+ T/H INPIPELINE ADC
D E C
10
OUTPUT DRIVERS
D9-D0
PD
REF
REF SYSTEM + BIAS
OVDD OGND
REFOUT REFIN REFP
COM REFN
OE
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference MAX1448
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V IN+, IN- to GND........................................................-0.3V to VDD REFIN, REFOUT, REFP, REFN, and COM to GND..........................-0.3V to (VDD + 0.3V) OE, PD, CLK to GND..................................-0.3V to (VDD + 0.3V) D9-D0 to GND.........................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 32-Pin TQFP (derate 11.1mW/C above +70C)...........889mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range ............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +3.0V, OVDD = +2.0V; 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND; VREFIN = +2.048V, REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential with respect to COM), CL 15pF at digital outputs (Note 5), fCLK = 83.3MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Input Differential Range Common-Mode Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS (fCLK = 83.3MHz, 4096-point FFT) fIN = 7.47MHz Signal-to-Noise Ratio SNR fIN = 20MHz fIN = 39.9MHz (Note 1) Signal-to-Noise Plus Distortion (up to 5th harmonic) fIN = 7.47MHz SINAD fIN = 20MHz fIN = 39.9MHz (Note 1) 55.8 55.3 56.5 56 59.1 59 58.5 59 58.8 58 dB dB fCLK 80 5.5 MHz Cycles VDIFF VCOM RIN CIN Switched capacitor load Differential or single-ended inputs 1.0 VDD/2 0.5 25 5 V V k pF INL DNL fIN = 7.47MHz fIN = 7.47MHz, no missing codes guaranteed 10 0.7 0.4 <1 0 2.2 1.0 1.7 2 Bits LSB LSB %FS %FS SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3.0V, OVDD = +2.0V; 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND; VREFIN = +2.048V, REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential with respect to COM), CL 15pF at digital outputs (Note 5), fCLK = 83.3MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Spurious-Free Dynamic Range SYMBOL fIN = 7.47MHz SFDR fIN = 20MHz fIN = 39.9MHz (Note 1) fIN = 7.47MHz Third-Harmonic Distortion Intermodulation Distortion Two-Tone Third-Order Intermodulation Distortion Total Harmonic Distortion (first 5 harmonics) Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time Differential Gain Differential Phase Output Noise INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation EXTERNAL REFERENCE Positive Reference Negative Reference Differential Reference Voltage REFIN Resistance DIGITAL INPUTS (CLK, PD, OE) CLK Input High Threshold VIH PD, OE 0.8 x VDD 0.8 x OVDD REFP REFN VREF RREFIN VREFIN = +2.048V VREFIN = +2.048V VREFP - VREFN, VREFIN = +2.048V 0.98 2.012 0.988 1.024 >50 1.07 V V V M REFOUT TCREF 2.048 1% 60 1.25 V ppm/C mV/mA IN+ = IN- = COM FPBW tAD tAJ For 1.5 x full-scale input HD3 fIN = 20MHz fIN = 39.9MHz (Note 1) IMDTT IM3 f1 = 24MHz at -6.5dB FS, f2 = 26MHz at -6.5dB FS (Note 2) f1 = 24MHz at -6.5dB FS, f2 = 26MHz at -6.5dB FS (Note 2) fIN = 7.47MHz THD fIN = 20MHz fIN = 39.9MHz (Note 1) Input at -20dB FS, differential inputs Input at -0.5dB FS, differential inputs CONDITIONS MIN 61 61 TYP 74 74 73 74 74 73 -74 -74 -72 -70 -69 500 400 1 2 2 1 0.25 0.2 MHz MHz ns psRMS ns % degrees LSBRMS -60 -60 dBc dBc dBc dBc dBc MAX UNITS
MAX1448
V
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3
10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference MAX1448
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3.0V, OVDD = +2.0V; 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND; VREFIN = +2.048V, REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential with respect to COM), CL 15pF at digital outputs (Note 5), fCLK = 83.3MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CLK Input Low Threshold VIL PD, OE Input Hysteresis Input Leakage Input Capacitance DIGITAL OUTPUTS (D9-D0) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Output Supply Voltage Analog Supply Current VDD OVDD IVDD Operating, fIN = 20MHz at -0.5dB FS Shutdown, clock idle, PD = OE = OVDD Operating, CL = 15pF, fIN = 20MHz at -0.5dB FS Shutdown, clock idle, PD = OE = OVDD Power-Supply Rejection TIMING CHARACTERISTICS CLK Rise to Output Data Valid OE Fall to Output Enable OE Rise to Output Disable CLK Pulse Width High CLK Pulse Width Low Wake-Up Time tDO tENABLE tDISABLE tCH tCL tWAKE Figure 6 (Note 3) Figure 5 Figure 5 Figure 6, clock period 12ns Figure 6, clock period 12ns (Note 4) 5 10 15 61 61 1.5 8 ns ns ns ns ns s PSRR Offset Gain 2.7 1.7 3.0 3.0 40 4 8 1 0.2 0.1 10 3.6 3.6 47 15 V V mA A mA A mV/V %/V VOL VOH ILEAK COUT ISINK = 200A ISOURCE = 200A OE = OVDD OE = OVDD 5 OVDD 0.2 10 0.2 V V A pF VHYST IIH IIL CIN VIH = VDD = OVDD VIL = 0 5 0.1 5 5 CONDITIONS MIN TYP MAX 0.2 x VDD 0.2 x OVDD V A pF UNITS
V
Output Supply Current
IOVDD
Note 1: SNR, SINAD, THD, SFDR and HD3 are based on an analog input voltage of -0.5dB FS referenced to a +1.024V full-scale input voltage range. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB better if referenced to the two-tone envelope. Note 3: Digital outputs settle to VIH,VIL. Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. Note 5: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL. 4 _______________________________________________________________________________________
10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference
Typical Operating Characteristics
(VDD = +3.0V, OVDD = +2.7V, internal reference, differential input at -0.5dB FS, fCLK = 83.3MHz, CL 10pF, TA = +25C, unless otherwise noted.)
FFT PLOT (fIN = 7.5MHz, 8192-POINT FFT, DIFFERENTIAL INPUT)
MAX1448-01
MAX1448
FFT PLOT (fIN = 20MHz, 8192-POINT FFT, DIFFERENTIAL INPUT)
MAX1448-02
UNDERSAMPLING FFT PLOT (fIN = 50MHz, 8192-POINT FFT, DIFFERENTIAL INPUT)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 2ND HARMONIC 3RD HARMONIC SFDR = 65.8dBc SNR = 58dB THD = -65.1dBc SINAD = 57.2dB
MAX1448-03
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25
SFDR = 75.5dBc SNR = 59.3dB THD = -73.9dBc SINAD = 59.2dB
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100
0
SFDR = 75.2dBc SNR = 59dB THD = -71.8dBc SINAD = 58.7dB 2ND HARMONIC 3RD HARMONIC
2ND HARMONIC 3RD HARMONIC
30
35
40
45
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT (fIN = 7.5MHz, 8192-POINT FFT, SINGLE-ENDED INPUT)
MAX1448-04
FFT PLOT (fIN = 20MHz, 8192-POINT FFT, SINGLE-ENDED INPUT)
MAX1448-05
TWO-TONE INTERMODULATION (8192-POINT IMD, DIFFERENTIAL INPUT)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 f1 = 24MHz AT -6.5dB FS f2 = 26MHz AT -6.5dB FS 3RD IMD = -74dBc
MAX1448-06
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25
SFDR = 72.2dBc SNR = 58.7dB THD = -70.8dBc SINAD = 58.4dB
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100
SFDR = 67.2dBc SNR = 58.6dB THD = -66.5dBc SINAD = 58dB
0
2ND HARMONIC 3RD HARMONIC
2ND HARMONIC 3RD HARMONIC
30
35
40
45
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
MAX1448-07
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
61 60 THD (dBc) SNR (dB) 59 58 57 56 55 54 -75 -80 1 10 ANALOG INPUT FREQUENCY (MHz) 100 1 SINGLE-ENDED DIFFERENTIAL -60 -65
MAX1448-08
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1448-09
80 75 70 SFDR (dBc) 65 60 55 50 45 40 1 10 ANALOG INPUT FREQUENCY (MHz) SINGLE-ENDED DIFFERENTIAL
62
-50 -55
SINGLE-ENDED -70 DIFFERENTIAL
100
10 ANALOG INPUT FREQUENCY (MHz)
100
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5
10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference MAX1448
Typical Operating Characteristics (continued)
(VDD = +3.0V, OVDD = +2.7V, internal reference, differential input at -0.5dB FS, fCLK = 83.3MHz, CL 10pF, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1448-10
FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY (SINGLE-ENDED)
MAX1448-11
SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY (SINGLE-ENDED)
VIN = 100mVp-p 4 2 AMPLITUDE (dB) 0 -2 -4 -6 -8
MAX1448-12
65
6 4 2
6
62 AMPLITUDE (dB)
SINAD (dB)
59
DIFFERENTIAL SINGLE-ENDED
0 -2 -4
56
53 -6 50 1 10 ANALOG INPUT FREQUENCY (MHz) 100 -8 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz)
1
10
100
1000
ANALOG INPUT FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 20MHz)
MAX1448-13
SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 20MHz)
MAX1448-14
TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 20MHz)
MAX1448-15
80 75 70 SFDR (dBc)
65
-50 -55 -60
60
SNR (dB)
55
THD (dBc)
65 60 55 50 -15 -12 -9 -6 -3 0 INPUT POWER (dB FS)
-65 -70
50
45
-75 -80 -15 -12 -9 -6 -3 0 -15 -12 -9 -6 -3 0 INPUT POWER (dB FS) INPUT POWER (dB FS)
40
SIGNAL-TO-NOISE PLUS DISTORTION vs. INPUT POWER (fIN = 20MHz)
MAX1448-16
SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE
MAX1448-17
SIGNAL-TO-NOISE RATIO vs. TEMPERATURE
fIN = 20MHz
MAX1448-18
65
84
fIN = 20MHz
70
60 SINAD (dB) SFDR (dBc)
80
66
50
72
SNR (dB) -40 -15 10 35 60 85
55
76
62
58
45
68
54
40 -15 -12 -9 -6 -3 0 INPUT POWER (dB FS)
64 TEMPERATURE (C)
50 -40 -15 10 35 60 85 TEMPERATURE (C)
6
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10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference
Typical Operating Characteristics (continued)
(VDD = +3.0V, OVDD = +2.7V, internal reference, differential input at -0.5dB FS, fCLK = 83.3MHz, CL 10pF, TA = +25C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION vs. TEMPERATURE
MAX1448-19
MAX1448
SIGNAL-TO-NOISE PLUS DISTORTION vs. TEMPERATURE
MAX1448-20
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (BEST STRAIGHT LINE)
MAX1448-21
-60
fIN = 20MHz
70
fIN = 20MHz
0.8 0.6 0.4
-64 SINAD (dB)
66
THD (dBc)
INL (LSB) -40 -15 10 35 60 85
-68
62
0.2 0 -0.2
-72
58
-76
54 -0.4
-80 -40 -15 10 35 60 85 TEMPERATURE (C)
50 TEMPERATURE (C)
-0.6 0 200 400 600 800 1000 1200 DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1448-22
GAIN ERROR vs. TEMPERATURE EXTERNAL REFERENCE (VREFIN = +2.048V)
MAX1448-23
OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = +2.048V)
MAX1448-24
0.4 0.3 0.2
0.05 0.04 0.03 GAIN ERROR (LSB) 0.02 0.01 0 -0.01 -0.02
3 2 OFFSET ERROR (LSB) 1 0 -1 -2 -3
DNL (LSB)
0.1 0 -0.1 -0.2 -0.3 -0.4 0 200 400 600 800 1000 1200 DIGITAL OUTPUT CODE
-0.03 -0.04 -0.05 -40 -15 10 35 60 85 TEMPERATURE (C)
-40
-15
10
35
60
85
TEMPERATURE (C)
ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
MAX1448-25
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX1448-26
DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE
fIN = 7.5MHz
MAX1448-27
47
47
12
45
44
10
IVDD (mA)
IVDD (mA)
43
41
IOVDD (mA) -40 -15 10 35 60 85
8
41
38
6
39
35
4
37 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60
32 TEMPERATURE (C)
2 1.6 2.0 2.4 2.8 3.2 3.6 OVDD (V)
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7
10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference MAX1448
Typical Operating Characteristics (continued)
(VDD = +3.0V, OVDD = +2.7V, internal reference, differential input at -0.5dB FS, fCLK = 83.3MHz, CL 10pF, TA = +25C, unless otherwise noted.)
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
MAX1448-28
ANALOG POWER-DOWN CURRENT vs. ANALOG POWER SUPPLY
MAX1448-29
DIGITAL POWER-DOWN CURRENT vs. DIGITAL POWER SUPPLY
PD = VDD, OE = OVDD
MAX1448-30
12
fIN = 7.5MHz
6
OE = OVDD, PD = VDD
10
10
5
8
IOVDD (mA)
IOVDD (A) 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60
IVDD (A)
8
4
6
6
3
4
4
2
2
2 -40 -15 10 35 60 85 TEMPERATURE (C)
1
0 1.2 1.8 2.4 OVDD (V) 3.0 3.6
SFDR, SNR, THD, SINAD vs. CLOCK FREQUENCY
MAX1448-31
INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE
MAX1448-32
85 80 SFDR, SNR, THD, SINAD (dB) 75
fIN = 25.12MHz
2.10
2.08 VREFOUT (V) SNR SINAD 55 50 70 75 80 85 90 95 100 CLOCK FREQUENCY (MHz) 2.00 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 2.02 SFDR THD
70 65 60
2.06
2.04
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1448-33
OUTPUT NOISE HISTOGRAM (DC INPUT)
129377
MAX1448-34
2.10
140000 120000 100000
2.08 VREFOUT (V)
COUNTS
2.06
80000 60000 40000
2.04
2.02 20000 2.00 -40 -15 10 35 60 85 TEMPERATURE (C) 0 0 N-2 965 N-1 N 730 N+1 0 N+2
DIGITAL OUTPUT NOISE
8
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10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference
Pin Description
PIN 1 2 3, 9, 10 4, 5, 8, 11, 14, 30 6 7 12 13 NAME REFN COM VDD GND IN+ INCLK PD FUNCTION Lower Reference. Conversion range is (VREFP - VREFN). Bypass to GND with a >0.1F capacitor. Common-Mode Voltage Output. Bypass to GND with a >0.1F capacitor. Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2F in parallel with 0.1F. Analog Ground Positive Analog Input. For single-ended operation, connect signal source to IN+. Negative Analog Input. For single-ended operation, connect IN- to COM. Conversion Clock Input Power-Down Input High: power-down mode Low: normal operation Output Enable Input High: digital outputs disabled Low: digital outputs enabled Three-State Digital Outputs D9-D5. D9 is the MSB. Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2F in parallel with 0.1F. Test Point. Do not connect. Output Driver Ground Three-State Digital Outputs D4-D0. D0 is the LSB. Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor-divider. Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a >0.1F capacitor. Upper Reference. Conversion range is (VREFP - VREFN). Bypass to GND with a >0.1F capacitor.
MAX1448
15 16-20 21 22 23 24-28 29 31 32
OE D9-D5 OVDD T.P. OGND D4-D0 REFOUT REFIN REFP
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9
10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference MAX1448
_______________Detailed Description
The MAX1448 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half clock-cycle. Counting the delay through the output latch, the clock-cycle latency is 5.5. A 1.5-bit (2-comparator) flash ADC converts the held input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. neously with S1, sampling the input waveform. S4a and S4b are then opened before S3a and S3b connect capacitors C1a and C1b to the amplifier output, and S4c is closed. The resulting differential voltage is held on C2a and C2b. The amplifier is used to charge C1a and C1b to the same values originally held on C2a and C2b. This value is then presented to the first-stage quantizer and isolates the pipeline from the fast-changing input. The wide-input-bandwidth T/H amplifier allows the MAX1448 to track and sample/hold analog inputs of high frequencies beyond Nyquist. Analog inputs (IN+ and IN-) can be driven either differentially or single-ended. It is recommended to match the impedance of IN+ and IN- and set the common-mode voltage to midsupply (VDD/2) for optimum performance.
Analog Input and Reference Configuration
The MAX1448 full-scale range is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The ADC's full-scale range is user-adjustable through the REFIN pin, which provides a high input impedance for this purpose. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered, low-impedance outputs.
INTERNAL BIAS S2a C1a
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuit in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuit samples the input signal onto the two capacitors (C2a and C2b) through S4a and S4b. S2a and S2b set the common mode for the amplifier input and open simultaMDAC VIN T/H x2 VOUT
COM S5a S3a
S4a IN+ OUT C2a S4c S1 OUT S4b C2b C1b
FLASH ADC 1.5 BITS
DAC
IN-
VIN
STAGE 1
STAGE 2
STAGE 10 S2b INTERNAL BIAS TRACK HOLD TRACK HOLD CLK INTERNAL NON-OVERLAPPING CLOCK SIGNALS S5b COM
S3b
DIGITAL CORRECTION LOGIC 10 D9-D0 VIN = INPUT VOLTAGE BETWEEN IN+ AND IN- (DIFFERENTIAL OR SINGLE-ENDED)
Figure 1. Pipelined Architecture--Stage Blocks 10
Figure 2. Internal Track-and-Hold Circuit
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10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference
The MAX1448 provides three modes of reference operation: * Internal reference mode * Buffered external reference mode * Unbuffered external reference mode In internal reference mode, the internal reference output (REFOUT) can be tied to the REFIN pin through a resistor (e.g., 10k) or resistor-divider if an application requires a reduced full-scale range. For stability purposes, it is recommended to bypass REFIN with a >10nF capacitor to GND. In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN. In this mode, REFOUT may be left open or connected to REFIN through a >10k resistor. In unbuffered external reference mode, REFIN is connected to GND, thereby deactivating the on-chip buffers of REFP, COM, and REFN. With their buffers shut down, these pins become high impedance and can be driven by external reference sources. ered as an analog input and routed away from any analog input or other digital signal lines. The MAX1448 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics. See Figures 3a, 3b, 4a, and 4b for the relationship between spurious-free dynamic range (SFDR), signal-to-noise ratio (SNR), total harmonic distortion (THD), or signal-to-noise plus distortion (SINAD) versus duty cycle.
MAX1448
Output Enable (OE), Power Down (PD), and Output Data (D0-D9)
All data outputs, D0 (LSB) through D9 (MSB), are TTL/CMOS-logic compatible. There is a 5.5 clock-cycle latency between any particular sample and its valid output data. The output coding is straight offset binary (Table 1). With OE and PD high, the digital outputs enter a high-impedance state. If OE is held low with PD high, the outputs are latched at the last value prior to the power down. The capacitive load on the digital outputs D0-D9 should be kept as low as possible (<15pF) to avoid large digital currents that could feed back into the analog portion of the MAX1448, degrading its dynamic performance. Using buffers on the ADC's digital outputs can further isolate the digital outputs from heavy capacitive loads. To further improve the MAX1448's dynamic performance, small series resistors (e.g., 100) may be added to the digital output paths, close to the ADC. Figure 5 displays the timing relationship between output enable and data output valid as well as powerdown/wake-up and data output valid.
Clock Input (CLK)
The MAX1448 CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the falling edge of the clock signal, mandating this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the ADC as follows: SNR = 20log (1 / 2fINtAJ) where fIN represents the analog input frequency, and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be consid-
System Timing Requirements
Figure 6 shows the relationship between the clock input, analog input, and data output. The MAX1448 samples at the falling edge of the input clock. Output
Table 1. MAX1448 Output Code for Differential Inputs
DIFFERENTIAL INPUT VOLTAGE* VREF x 511/512 VREF x 510/512 VREF x 1/512 0 - VREF x 1/512 - VREF x 511/512 - VREF x 512/512 DIFFERENTIAL INPUT +Full Scale -1LSB +Full Scale -2LSB +1LSB Bipolar Zero -1LSB Negative Full Scale + 1LSB Negative Full Scale STRAIGHT OFFSET BINARY 11 1111 1111 11 1111 1110 10 0000 0001 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000
*VREF = VREFP = VREFN ______________________________________________________________________________________ 11
10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference MAX1448
100 fIN = 25.12MHz AT -0.5dB FS -50 -55 90 -60 SFDR (dBc) THD (dBc) 80 -65 -70 -75 60 -80 50 20 30 40 50 60 70 CLOCK DUTY CYCLE (%) -85 20 30 40 50 60 70 CLOCK DUTY CYCLE (%) fIN = 25.12MHz AT -0.5dB FS
70
Figure 3a. Spurious Free Dynamic Range vs. Clock Duty Cycle (Differential Input)
Figure 4a. Total Harmonic Distortion vs. Clock Duty Cycle (Differential Input)
64 62 60
fIN = 25.12MHz AT -0.5dB FS
64 62 60 SINAD (dB) 58 56 54 52
fIN = 25.12MHz AT -0.5dB FS
SNR (dB)
58 56 54 52 20 30 40 50 60 70 CLOCK DUTY CYCLE (%)
20
30
40
50
60
70
CLOCK DUTY CYCLE (%)
Figure 3b. Signal-to-Noise Ratio vs. Clock Duty Cycle (Differential Input)
Figure 4b. Signal-to-Noise Plus Distortion vs. Clock Duty Cycle (Differential Input)
data is valid on the rising edge of the input clock. The output data has an internal latency of 5.5 clock cycles. Figure 6 also shows the relationship between the input clock parameters and the valid output data.
Applications Information
Figure 7 shows a typical application circuit containing a single-ended to differential converter. The internal reference provides a VDD/2 output voltage for level shifting purposes. The input is buffered and then split to a volt-
age follower and inverter. A lowpass filter follows the op amps to suppress some of the wideband noise associated with high-speed op amps. The user may select the RISO and CIN values to optimize the filter performance to suit a particular application. For the application in Figure 7, an RISO of 50 is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor.
12
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10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent solution for converting a single-ended source signal to a fully differential signal, required by the MAX1448 for optimum performance. Connecting the transformer's center tap to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, may also improve the overall distortion. In general, the MAX1448 provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower since both inputs (IN+, IN-) are balanced, and each of the inputs only requires half the signal swing compared to single-ended mode.
OE
Single-Ended AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended application. The MAX4108 op amp provides high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal.
MAX1448
Grounding, Bypassing, and Board Layout
The MAX1448 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1F ceramic capacitors and a 2.2F bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider
tENABLE OUTPUT DATA D9-D0 HIGH-Z
tDISABLE HIGH-Z
VALID DATA
Figure 5. Output Enable Timing
5.5 CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6
ANALOG INPUT
CLOCK INPUT tD0 N-6 N-5 N-4 tCH N-3
tCL N-2 N-1 N N+1
DATA OUTPUT
Figure 6. System and Output Timing Diagram ______________________________________________________________________________________ 13
10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference MAX1448
+5V
0.1F LOWPASS FILTER MAX4108 300 0.1F RISO 50 0.1F CIN 22pF IN+
-5V
MAX1448
600 300 600 COM 0.1F +5V +5V 0.1F INPUT 0.1F MAX4108 300 0.1F MAX4108 INRISO 50 0.1F CIN 22pF LOWPASS FILTER 600
-5V
300 -5V
300 300 600
Figure 7. Typical Application Circuit Using the Internal Reference
using a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC's package. The two ground planes should be joined at a single point so that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes that produces optimum results. Make this connection with a low-value, surface-mount resistor (1 to 5), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output
14
buffer or DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces. Keep all signal lines short and free of 90 turns.
Static Parameter Definitions
Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified. The MAX1448's static linearity parameters are measured using the best straight-line fit method.
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10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference
25 IN+ 22pF 0.1F VIN 1 N.C. 2 3 T1 6 5 4 2.2F 0.1F MAX1448
Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 10). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum A/D noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR(MAX) = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB is computed from: ENOB = (SINAD - 1.76dB) / 6.02dB
MAX1448
COM
MINICIRCUITS TT1-6 25 IN22pF
Figure 8. Using a Transformer for AC Coupling
Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter Figure 10 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
REFP
VIN MAX4108 100
1k 0.1F RISO IN+ CIN 1k
MAX1448
COM 0.1F RISO
REFN
100 RISO = 50 CIN = 22pF
INCIN
Figure 9. Single-Ended AC-Coupled Input
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15
10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference MAX1448
CLK
Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale, and their envelope is at -0.5dB full scale.
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
___________________Chip Information
T/H TRACK HOLD TRACK
TRANSISTOR COUNT: 5684 PROCESS: CMOS
Figure 10. Track-and-Hold Aperture Timing
Pin Configuration
REFOUT
Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the input signal's first five harmonics to the fundamental itself. This is expressed as: THD = 20 x log
TOP VIEW
REFIN REFP GND
D0
D1
D2 26
32 REFN COM VDD GND GND IN+ INGND 1 2 3 4 5 6 7 8 9 VDD
31
30
29
28
27
( (V
2 2 2 2 2 + V3 + V4 + V5 ) / V1
)
D3 25 24 D4 23 OGND 22 T.P. 21 OVDD 20 D5 19 D6 18 D7 17 D8 16 D9
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
MAX1448
10 VDD
11 GND
12 CLK
13 PD
14 GND
15 OE
TQFP
16
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10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference
Package Information
32L,TQFP.EPS
MAX1448
E
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17
10-Bit, 80Msps, Single +3.0V, Low-Power ADC with Internal Reference MAX1448
Package Information (continued)
E
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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